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Subramaniam, Jayasri
- LEACH-E: AN ENERGY-EFFICIENT CLUSTERING PROTOCOL FOR IMPROVING THE INTER-CLUSTER COMMUNICATION OF WIRELESS SENSOR NETWORKS
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PDF Views:106
Authors
Affiliations
1 Jamia Millia Islamia, IN
2 Galgotias University, IN
3 University of Northampton, GB
1 Jamia Millia Islamia, IN
2 Galgotias University, IN
3 University of Northampton, GB
Source
ICTACT Journal on Communication Technology, Vol 12, No 1 (2021), Pagination: 2290-2293Abstract
Wireless Sensor Networks (WSN) comprises distributed sensors that are used to measure items. Lowering battery power for both the sensor would shorten its working life. It is also necessary to increase the lifetime of sensors because it will affect the network speed of information transmission. By using low-energy adaptive clustering, energy can be managed to a certain extent in an intelligent network (LEACH). The key notion of this upgraded algorithm would be to compare the entire location and the existing energy of the node. The new method of attack, known as LEACH-E Improving hierarchical routing can allow operations to progress. Since the improvement of CH selection techniques and the LEACH performs optimally.Keywords
Cluster Communication, Wireless Sensor Networks, LEACH-E, and Energy Efficiency.Full Text
References
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- CMOS Based Driver Tree Design for Microprocessor Clock Distribution Units Iin Biomedical Image Processing Circuits
Abstract Views :130 |
PDF Views:0
Authors
V. Sujatha
1,
S. Ravindrakumar
2,
D. Sasikala
3,
V. M. Senthil Kumar
4,
N. V. Kousik
5,
Jayasri Subramaniam
6
Affiliations
1 Department of Electronics and Communication Engineering, Shree Sathyam College of Engineering and Technology, IN
2 Department of Biomedical Engineering, Sri Shakthi Institute of Engineering and Technology, IN
3 Department of Electronics and Communication Engineering, Muthayammal Engineering College, IN
4 Department of Electronics and Communication Engineering, Malla Reddy College of Engineering and Technology, IN
5 Department of School of Computing Science and Engineering, Galgotias University, IN
6 Division of Computing, University of Northampton, GB
1 Department of Electronics and Communication Engineering, Shree Sathyam College of Engineering and Technology, IN
2 Department of Biomedical Engineering, Sri Shakthi Institute of Engineering and Technology, IN
3 Department of Electronics and Communication Engineering, Muthayammal Engineering College, IN
4 Department of Electronics and Communication Engineering, Malla Reddy College of Engineering and Technology, IN
5 Department of School of Computing Science and Engineering, Galgotias University, IN
6 Division of Computing, University of Northampton, GB
Source
ICTACT Journal on Microelectronics, Vol 7, No 1 (2021), Pagination: 1080-1084Abstract
The transmission of clock signal is done across the integrated circuit in the presence of buffers and wires in synchronous biomedical systems on-chip architectures. This paper presents the investigation of the driver tree architecture to be used in microprocessor and DSP processors for biomedical image processing applications for clock distribution. In system on chip architecture this design plays an important role. Several clock distribution units like parallel, H-Bridge configurations were implemented in past. A new buffer is designed for the improvement of driving capability in clock distribution. This paper presents the CMOS based clock distribution circuit with better power and drive current. The parameters like power and current are investigated. Predictive technology models for CMOS 90nm technology are used.Keywords
CMOS, Current Driver, Clock Driver, H-Bridge, Buffer, Power.
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- Mathematical Morphology based Digital Image Enhancement Processing with Cross Separate Boundary Objects
Abstract Views :111 |
PDF Views:1
Authors
Affiliations
1 Department of Computer Science, The Quaide Milleth College for Men, IN
2 Indian Institute of Information Technology, Kalyani, IN
3 Department of Master of Science in Computing, University of Northampton, GB
1 Department of Computer Science, The Quaide Milleth College for Men, IN
2 Indian Institute of Information Technology, Kalyani, IN
3 Department of Master of Science in Computing, University of Northampton, GB
Source
ICTACT Journal on Image and Video Processing, Vol 12, No 4 (2022), Pagination: 2699-2703Abstract
In computer science, digital image processing is the use of computer algorithms to perform image processing on digital images. The Image processing as a subgroup or background of digital signal processing has many advantages over analog image processing. The Digital image processing allows the use of a wide range of algorithms for input data and avoids problems such as noise accumulation and signal distortion during the processing process. Because images are defined in two dimensions (perhaps more than two dimensions), image processing can be formatted into multi-dimensional systems. In this paper an effective Mathematical morphology model was proposed to enhance the quality of images. In this mode, the image is pre-processed and then the gradient is changed using a mathematical image system. Then, the edges are detected by the margin detection method based on the statistical data. This method removes the shadow contours caused by the lights, directly separates the boundaries of the objects and has an impact on the background noise suppression.Keywords
Digital Image Processing, Computer Algorithms, Digital Images, Mathematical MorphologyReferences
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